Tag Archives: FPGA

Papilio One: 4 bit binary counter

FPGA implementation of a 4 bit binary counter. Hardware was described using VHDL. The Papilio One comes with a 32 MHz clock but this was divided down to 0.5Hz so you could actually see the counter counting. VHDL code: The … Continue reading

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Papilio One FPGA board , using a switch to turn on an LED

Put this together just to start learning a bit about VHDL coding. The logic is simple, if input P4 (the switch) is low, output P3 (the LED) is high, and vice versa. The circuit diagram is shown below:

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Flashing an LED using a Papilio One FPGA development board

It took three hours of hardship to get this far. Documenting the process to save my future self / someone else going through this simple but convoluted process.

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