fast documentation of hardware and software projects
FPGA implementation of a 4 bit binary counter. Hardware was described using VHDL. The Papilio One comes with a 32 MHz clock but this was divided down to 0.5Hz so you could actually see the counter counting. VHDL code: The LEDs were just thrown on a bit a stripboard like so (with 0805 resistors soldered…
To flash an LED at a specific frequency we need to divide the input clock frequency. In VHDL this can be done using counters. The Papilio One FPGA board comes with a 32MHz oscillator. 32Mhz means 32 million pulses per second, if you wanted to divide this down to 1Hz you could just set an…
Put this together just to start learning a bit about VHDL coding. The logic is simple, if input P4 (the switch) is low, output P3 (the LED) is high, and vice versa. The circuit diagram is shown below:
It took three hours of hardship to get this far. Documenting the process to save my future self / someone else going through this simple but convoluted process.