
Papilio One: 4 bit binary counter
FPGA implementation of a 4 bit binary counter. Hardware was described using VHDL. The Papilio One comes with a 32 MHz clock but this was divided down to 0.5Hz so you could actually see the counter counting. VHDL code: The LEDs were just thrown on a bit a stripboard like so (with 0805 resistors soldered…