Papilio One: 4 bit binary counter

FPGA implementation of a 4 bit binary counter. Hardware was described using VHDL. The Papilio One comes with a 32 MHz clock but this was divided down to 0.5Hz so you could actually see the counter counting.

VHDL code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

entity counter is
port(
L0,L1,L2,L3: out std_logic := '0';
i_clk	: in std_logic := '0';
i_num	: inout std_logic_vector (3 downto 0) := (others => '0')

);
end counter;

architecture behaviour of counter is

--count to 32 million for 0.5Hz
constant c_CNT_1HZ   : natural := 32000000;

--this signal acts as the counter
signal r_CNT_1HZ   : natural range 0 to c_CNT_1HZ;

--this signal will toggle at 1Hz
signal r_TOGGLE_1HZ : std_logic := '0';

begin

p_1_Hz : process(i_clk) is
begin
if rising_edge(i_clk) then
if r_CNT_1HZ = c_CNT_1HZ then
r_TOGGLE_1HZ <= not r_TOGGLE_1HZ;
r_CNT_1HZ    <= 0;
else
r_CNT_1HZ <= r_CNT_1HZ + 1;
end if;
end if;
end process p_1_HZ;

--counter
process(r_TOGGLE_1Hz)
begin
if rising_edge(r_TOGGLE_1HZ) then
if i_num = "1111" then
i_num <= (others => '0');

else
i_num <= i_num + '1';
end if;

if i_num(0) = '1' then
L0 <= '1';
else
L0 <= '0';
end if;

if i_num(1) = '1' then
L1 <= '1';
else
L1 <= '0';
end if;

if i_num(2) = '1' then
L2 <= '1';
else
L2 <= '0';
end if;

if i_num(3) = '1' then
L3 <= '1';
else
L3 <= '0';
end if;

end if;
end process;

end behaviour;

The LEDs were just thrown on a bit a stripboard like so (with 0805 resistors soldered on underneath):

Circuit Diagram:

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Shane Ormonde